The following semiconductor devices are known as semiconductor devices whose circuits are composed by nonvolatile memory field-effect transistors. Here, “nonvolatile” means that information representing an on-off state of a field-effect transistor does not disappear even when a power source potential becomes zero.
As a first conventional art, a nonvolatile memory cell array configured by arranging a plurality of memory cells of a six-transistor type SRAM, lengthwise and crosswise in a form of a matrix has been suggested: each of the memory cells is constituted by a combination of a complementary inverter latch circuit which includes a total of four field-effect transistors of two n-channel field-effect transistors and two p-channel field-effect transistors in which a ferroelectric layer with a memory holding function is disposed in a gate insulating structure, and two field-effect transistors in which a gate insulating structure does not have a memory holding function of data writing and reading added thereto (for example, see Patent Document 1).
As a second conventional art, a device in which a complementary inverter circuit which includes two field-effect transistors of an n-channel type and a p-channel type in which a ferroelectric layer with a memory holding function is disposed in a gate insulating structure is arranged, and an electric potential of a certain critical node point is stored and held in the complementary inverter circuit in advance during operation of the circuit so that data can be restored rapidly when electric power is abruptly turned off has been suggested (for example, Patent Document 2).
As a third conventional art, a nonvolatile memory sequence circuit which is a latch circuit or a flip-flop circuit which includes a complementary inverter circuit constituted by two field-effect transistors of an n-channel type and a p-channel type in which a ferroelectric layer with a memory holding function is disposed in a gate insulating structure has been suggested (for example, Patent Document 3).
As a fourth conventional art, a nonvolatile memory cell array in which, in order to avoid erroneous writing and reading, using a pair of an n-channel field-effect transistor in which a ferroelectric layer with a memory holding function is disposed in a gate insulating structure and a diode device as a unit of a memory cell, the memory cells are arranged lengthwise and crosswise in the form of a matrix, and a well is separated in a direction perpendicular to a word line, so that a substrate potential can be obtained independently for each column has been suggested (for example, Patent Document 4).
First, problems of the first to third conventional arts will be described below.
The first to third conventional arts attempt to perform nonvolatile memory writing into the complementary circuit in which both the n-channel field-effect transistor and the p-channel field-effect transistor in which the ferroelectric layer is disposed in the gate insulating structure are used in such a way that a connection between gate terminals of the field-effect transistors of the two types is used as an input terminal, and a connection between drain terminals thereof is used an output terminal. In the first to third conventional arts, when memory writing into the complementary circuit is performed, if an input to the gate terminal has a high electric potential (H), an electric potential difference between the gate terminal and the source terminal of the p-channel field-effect transistor of the two field-effect transistors which constitute the complementary circuit becomes 0; while if an input to the gate terminal has high electric potential (H) has a low electric potential (L), an electric potential difference between the gate terminal and the source terminal of the n-channel field-effect transistor becomes 0 V. In a complementary circuit in which a connection between gate terminals of the two field-effect transistors of the n-channel type and the p-channel type, which are not limited to the field-effect transistor in which the ferroelectric layer is disposed in the gate insulating layer, is used as an input terminal, and a connection between drain terminals thereof is used an output terminal, in order to try to improve the efficiency of circuit design, for example, to greatly decrease the number of power source potentials necessary for operation and to decrease the number of power source potential generating circuits and the number of power source wirings, the operation of the complementary circuit is performed in a state in which a source terminal and a substrate terminal of the p-channel field-effect transistor have the same electric potential and a source terminal and a substrate terminal of the n-channel field-effect transistor have the same electric potential. However, in the field-effect transistor in which the ferroelectric layer is disposed in the gate insulating structure, the electric potential of 0 V between the gate terminal and the substrate terminal is too insufficient to perform a proper nonvolatile memory holding operation. Therefore, in the first to third conventional arts, either to accept an insufficient nonvolatile memory state by having a substrate terminal of the n or p-channel field-effect transistor comprising the ferroelectric layer disposed in the gate insulating structure having the same electric potential as a source terminal thereof or to increase the number of power source potentials in order to control an electric potential of the substrate terminal independently of the source terminal has to be selected. In the former case, reliability of the nonvolatile memory state deteriorates, and in the later case, there is a problem in that not only the number of power source potentials is increased, but also there is a problem in that circuit design is inefficient, and the circuit area size increases since it is necessary to prepare a separate well in order to divide a well potential of a circuit which performs a nonvolatile memory operation and a well potential of a circuit which does not perform a nonvolatile memory operation.
The former case will be described in further detail using a case in that a circuit performing a nonvolatile memory operation, that is, a main stage circuit, is a NOT logic circuit shown in FIGS. 3(a) and 3(b) in which two nonvolatile memory field-effect transistors of an n-channel type (FIG. 1) and a p-channel type (FIG. 2) are constituted in a complementary form.
Here, a high potential power source is Vcc1, and a low potential power source is Vss1. Therefore, in FIG. 3(b), Vcc=Vcc1, and Vss=Vss1. When an output of a preceding stage is High, that is, Vcc1, Vcc1 is applied to a gate terminal of the main stage, that is, A2 of FIG. 3(b). At this time, the n-channel nonvolatile memory field-effect transistor n-Tr2 of the main stage circuit is in a state A of FIG. 4(a), and the p-channel nonvolatile memory field-effect transistor p-Tr2 of the main stage circuit is in a state A′ of FIG. 4(b). That is, an electric potential difference Vcc1−Vss1 between a gate terminal and a p-type substrate terminal which has an absolute value large sufficiently to write a nonvolatile ON state is applied to n-Tr2, so that an electric current Ids1Na between a gate terminal and a source terminal which has a sufficiently large absolute value flows, while an electric potential difference of Vcc1−Vss1=0 V between a gate and an n-type substrate terminal is applied to p-Tr2, and it does not become a sufficient OFF state and so an electric current Ids1Pb between a drain terminal and a source terminal of FIG. 4(b) flows.
In the next memory holding state, that is, in a state in which both a power source potential of the preceding stage and a power source potential of the main stage become zero, a state B of FIG. 4(a), that is, a channel resistance corresponding to an electric current Ids1Nb between the drain terminal and the source terminal is stored and held in n-Tr2. Meanwhile, the state A′ of FIG. 4(b), that is, a channel resistance corresponding to an electric current Ids1Pb between the drain terminal and the source terminal is stored and held in p-Tr2.
Next, when power source potentials Vcc1 and Vss1 of the main stage circuit are restored, that is, when the memory holding state is released, an output terminal B2 of the main stage circuit of FIG. 3(b) outputs any intermediate potential between Vcc1 and Vss1. In the case of Ids1Nb>Ids1Pb, an intermediate potential slightly inclining toward Vss1 is output, so that, of two values of High and Low, a right logical state Low can be barely output to B2, but in the case of Ids1Nb<Ids1Pb, an intermediate potential slightly inclining toward Vcc1 is output, so that a wrong logic state High is output to B2.
Similarly, when an output of the preceding stage is Low, that is, Vss1, Vss1 is input to the gate terminal A2 of the main stage of FIG. 3(b). At this time, n-Tr2 is in the state B of FIG. 4(a), and p-Tr2 is in the state B′ of FIG. 4(b). An electric potential difference Vss1−Vcc1 between the gate terminal and the n-type substrate terminal which has an absolute value sufficiently large to write a nonvolatile ON state is applied to p-Tr2, so that an electric current Ids1Pa between the drain terminal and the source terminal which has a sufficiently large absolute value flows, while an electric potential difference of Vss1−Vss1=0 V between the gate terminal and the p-type substrate terminal is applied to n-Tr2, and it does not become a sufficient OFF state, so that an electric current Ids1Nb between the drain terminal and the source terminal of FIG. 4(a) flows.
In the next memory holding state, that is, in a state in which both a power source potential of the preceding stage and a power source potential of the main stage become zero, the state B of FIG. 4(a), that is, a channel resistance corresponding to an electric current Ids1Nb between the drain terminal and the source terminal is stored and held in n-Tr2. Meanwhile, the state A′ of FIG. 4(b), that is, a channel resistance corresponding to an electric current Ids1Pb between the drain terminal and the source terminal is stored and held in p-Tr2.
Next, when the power source potentials Vcc1 and Vss1 of the main stage circuit are restored, that is, when the memory holding state is released, the output terminal B2 of the main stage circuit outputs any intermediate potential between Vcc1 and Vss1. In the case of Ids1Nb<Ids1Pb, an intermediate potential slightly inclining toward Vcc1 is output, so that, out of two values of High and Low, a right logical state High can be barely output to B2, but in the case of Ids1Nb>Ids1Pb, an intermediate potential slightly inclining toward Vss1 is output, so that a wrong logic state Low is output to B2. Since the relationship of magnitude of Ids1Nb and Ids1Pb is previously determined according to device characteristics of n-Tr2 and p-Tr2, either of a state in which n-Tr2 is turned on and p-Tr2 is turned off and a state in which n-Tr2 is turned off and p-Tr2 is turned on is wrongly read.
For the foregoing reasons, in the first to third conventional arts, any one of logical states High and Low cannot be properly retained in the output terminal of the complementary nonvolatile memory circuit and thus cannot be read again.
Next, a problem of the fourth conventional art will be described.
In the fourth conventional art, it is difficult to prevent erroneous writing for cells other than a memory cell of a selected crossing point. Random access is commonly performed by selecting one word line which electrically connects gate terminals of nonvolatile memory field-effect transistors which constitute memory cells disposed on the same column of a memory array and one well potential line which electrically connects substrate terminals of nonvolatile memory field-effect transistors disposed on the same row of a direction perpendicular to the word line. When nonvolatilely writing data in a memory cell which includes a nonvolatile memory field-effect transistor, a high electric potential needs to be sufficiently applied between a gate terminal and a substrate terminal of the field-effect transistor. However, in the fourth conventional art, since a high electric potential is equally applied to cells connected to the same word line or cells connected to the same well potential line, in order to prevent erroneous writing for cells other than a memory cell of a selected crossing point, an electric potential which mitigates an electric potential difference between a gate terminal and a substrate terminal of a nonvolatile memory field-effect transistor of a non-selected cell is appropriately applied to all word lines other than a selected word line or all well potential lines other than a selected well potential line. However, when a memory window of a nonvolatile memory field-effect transistor which constitutes a memory cell is not sufficiently large, this method is difficult to perform nonvolatile memory writing for a selected cell while preventing erroneous writing for a non-selected cell.    Patent Document 1: Japanese Patent Application Laid-Open No. 5-250881    Patent Document 2: Japanese Patent Application Laid-Open No. 2000-323671    Patent Document 3: Japanese Patent Application Laid-Open No. 2000-77986    Patent Document 4: Japanese Patent Application Laid-Open No. 2001-110192